\subsubsection{Cross Layer Optimization}
The effectiveness of the circuit and architecture techniques 
developed in this research will be enhanced by adopting a
device-circuit co-optimization approach. The new flip-flop 
topologies will be designed considering the architectural
requirements for RAZOR and ReCycle. The characteristics of 
the TFET-based flip-flops and other standard cells, including the 
effect of process variations will define the design specifications 
for the architectural techniques. Reduction in design margins 
achieved by RAZOR and ReCycle will be leveraged to 
design circuits for higher energy efficiency by re-optimizing 
the voltage of operation and the transistor widths. 
The benefits of the proposed co-design approach will be 
evaluated by comparing the power/performance of the optimized 
TFET and FinFET based processors.